邊界掃描技術在板級可測性設計中的應用
閱讀：206發布時間：2008-01-17
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煙臺勾股通信技術有限公司
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摘 要：硬件系統的規模越來越大，復雜程度越來越高, 對其進行測試也越來越困難，邊界掃描技術很好地解決了傳統測試的不足。闡述了JTAG技術的基本原理，從設計方法、優化策略及實現技術等方面，對基于JTAG的PCB可測性設計進行了研究，給出了具體的實現方法，并實現了自動測試系統中數據采集電路板的可測性設計。結果證明該方法有效縮短了測試時間,降低了維修測試費用,具有較大的實用價值。
關鍵詞：電路板；邊界掃描；板級測試；可測性設計；JTAG
中圖分類號：TP311 文獻標識碼：A 文章編號：1672-4984（2007）04-0077-04
Application of boundary scan technique in design of board-level test
ZHOU Jie， ZHOU Shao-lei， PENG Xian， LEI Ming
（Department of Control Engineering，Naval Aeronautical Engineering Academy，Yantai 264001，China）
Abstract: As the scale and complexity of hardware systems increase quickly,
test becomes a difficult task. The BST technique can well make up the shortcoming
of traditional test techniques. This article presented the basic principle of JTAG
technique. The design for test of PCB based on JTAG was researched from designed
method, optimization strategy, realization technique and so on. Some concrete
implementing methods were given and the realization of the measurability design
of the data collection circuit board of an automatic test system was also presented.
The result shews that, by using this method, th time of test can be effectively
shortened and the cost of maintenance and test can be reduced.
Key words: PCB； Boundary scan； Board level test； Design for test； JTAG
